Verification Engineer at SmartDV Technologies passionate about SystemVerilog, UVM, Digital Design, Flutter Development and AI-powered applications.
Hello! I'm Paramasivam, a Verification Engineer at SmartDV Technologies with a Bachelor's degree in Electronics and Communication Engineering. I enjoy building reliable hardware verification environments using SystemVerilog and UVM, while also exploring software development with Flutter, Firebase, and Artificial Intelligence. I love solving real-world engineering problems, learning new technologies, and creating impactful applications.
Paramasivam
paramasivamsk2811@gmail.com
Bengaluru, India
Verification Engineer
Hybrid Deep Learning model for detecting multiple scalp diseases using Transfer Learning and image classification.
Blog application with Firebase Authentication, Admin Panel, Likes, Comments and User Profiles.
ERP platform for Student Management, Attendance, Fees and Reports.
Responsive personal portfolio showcasing projects, experience and technical skills.
Console based reservation system developed in C with ticket booking and management.
Cisco Packet Tracer based network security project implementing intrusion prevention.
Mepco Schlenk Engineering College
Sivakasi, Tamil Nadu
Computer Science
SAV Balakrishna Matric Hr. Sec School
SAV Balakrishna Matric School
Projects Completed
Professional Certifications
Years of Learning in Verification
Passion for Technology
I'm always open to discussing Verification, SystemVerilog, UVM, Flutter projects, or exciting opportunities.